In this edition of the newsletter, I will continue discussing the use of Python for Design Verification.

In the last newsletter, we simulated a Cocotb-based testbench to verify a simple D flip-flop RTL. In this post we take a step ahead and complete our last Cocotb based testbench.

The above RTL implements a standard D-ff using the d pin as the input port and the q pin as the output. This is implemented using the always_ff block using the non-blocking assignments.

And this is what we had for our python based testbench using Cocotb:​
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The above testbench creates a single test called dff_simple_test which randomly drives values on the d input of the design. The testbench also creates a 10us clock and drives it to the DUT. However, the testbench today lacks the capability to check the q pin output from the DUT. Let's see how can we extend the testbench to add this checker:

As you can see we've introduced a new python variable called expected_val which basically computes the expected result for the current cycle and compares it with the DUT output. The following line does the comparison and raises an error if the assert fails:

This is done for every clock cycle (notice that the check is added in the python for loop) and as well as for the last clock cycle before the simulation ends. This would be a good point to stop and try the running the updated TB. However, it is always advisable to ensure that the check actually fires if something goes incorrect. I would recommend introducing an error in the RTL in the and run it against the updated Cocotb testbench to see the testcase failing.

Well, that's it for this edition of the SiliconNotes. In the next edition, we would cover is Logging

Have a great week!
Rahul

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