SiliconNotes

SiliconNotes Read on web → Have you ever wondered on when would you want to use an `assign` statement or when would you want to write the combinational logic using an `always_comb` block? Well, generally you can do either but if you have seen my solutions part of the Hands-on RTL Design course then you'd know that I like to use `assign` (by combining it with `genvar` loop) a lot more and very specifically use the `always_comb` block. One of the reasons for it is because I really like to be...

SiliconNotes Read on web → Ever since launching the Hands-on RTL Design course on the QuickSilicon platform, I’ve been approached by many users from different backgrounds about how the course has helped them in their careers: Fresh graduates have used the course to enhance their resumes by showcasing stronger project work, while also deepening their understanding of RTL Design and Synthesis. Seasoned RTL Design and Verification engineers have taken the course to better prepare for interviews...

SiliconNotes Read on web → Ever since launching synthesis support on the QuickSilicon platform, I’ve been testing some of the submitted problems with it. I’m happy to see that many of them passed the synthesis checks — but here are the top 3 gotchas I discovered: Inferred Latch The infamous inferred latch due to missing driving a signal in all the possible arcs of the always_comb block: Inferred Latch Inconsistent Reset Polarity This one is hard to catch but the sequential block (dff here)...

SiliconNotes Read on web → It passes all the tests, but I don’t know if my RTL is synthesizable! Surprisingly, this has been one of the most frequently asked questions for problems on the QuickSilicon platform. I understand that for someone new to RTL Design, it’s important to have some way to verify that their RTL is synthesizable and doesn’t include verification-only SystemVerilog constructs. To help with this, we’re soon launching a new feature that lets you synthesize your RTL right on...

SiliconNotes Read on web → I’ve just released my mock interview with a Senior RTL Design Engineer on YouTube. In this video, I conduct a mock RTL Design interview with a Senior RTL Design Engineer working at a leading tech company. This is a great resource if you’re preparing for hardware interviews and want a behind-the-scenes look at how real design questions are approached. 🚀 RTL Design Problems Discussed in the Interview • Round Robin Arbiter • Single Copy Atomic Counter Mock RTL Design...

SiliconNotes Read on web → For the past few months, I’ve been running a personalized mentorship program focusing on RTL Design and Verification. It has been super helpful for professionals looking to upskill in their careers. I thought it would be wise to announce the program here now that I have more idea on how to run it and have improved the program a lot over the last few months! Here’s a gist of what it contains: This 1:1 personalised program is customised to deliver exactly what you...

SiliconNotes Read on web → The second episode of my video podcast series is out now! 🎥I wanted to make the most of my LinkedIn network — and what better way than hosting video podcasts with industry experts to share their journeys and insights?In this episode, I chat with Kay Li, Co-founder & CEO of Silogy, where he’s building the first AI Verification Engineer to accelerate chip verification workflows.We talk about his journey learning chip design after completing a mathematics degree from...

SiliconNotes Read on web → I spent the weekend interviewing a Staff RTL Design Engineer — here’s a sneak peek! I’m currently editing the interview and will be uploading it to my YouTube channel soon! Oh, and before I forget — I’m also making steady progress on the Hands-on Testbench Design course. I’m excited to see how this one turns out! Have a great week!Rahul Hands-on RTL Design - QuickSilicon RISC-V Processor Design - QuickSilicon Subscribe on YouTube Schedule your Mock RTL Design...

SiliconNotes Read on web → As you all might be aware, I am working on releasing a new course on the QuickSilicon platform. This course will focus on teaching concepts related to modern testbench design. I have most of the exercises and modules coded and have started recording the video lessons. I wanted to give you a quick sneak peek into what’s coming by sharing a pre-release version of the course introduction video. Here it is: I’ve been working hard to put this course together — focused on...