Ever since launching synthesis support on the QuickSilicon platform, I’ve been testing some of the submitted problems with it.
I’m happy to see that many of them passed the synthesis checks — but here are the top 3 gotchas I discovered:
Inferred Latch
The infamous inferred latch due to missing driving a signal in all the possible arcs of the always_comb block:
Inferred Latch
Inconsistent Reset Polarity
This one is hard to catch but the sequential block (dff here) constructed here uses inconsistent reset polarity. The always_ff block is triggered using the negedge of the reset signal while the logic assumes a posedge reset.
Inconsistent Reset Polarity
Internal Signal as loop index
I noticed this error a lot especially with the LRU problem. A lot of submitted code (some of them passed all the testcases) used internal RTL signals as loop variables!
Internal Signal as loop index
Oh, and before I forget — I’m also making steady progress on the Hands-on Testbench Design course. I’m excited to see how this one turns out!