It passes all the tests, but I don’t know if my RTL is synthesizable!

Surprisingly, this has been one of the most frequently asked questions for problems on the QuickSilicon platform. I understand that for someone new to RTL Design, it’s important to have some way to verify that their RTL is synthesizable and doesn’t include verification-only SystemVerilog constructs.

To help with this, we’re soon launching a new feature that lets you synthesize your RTL right on the platform. The initial version will include support for running synthesis (using Yosys!) and reporting whether the design passes or fails.

This will give you a quick check to see if your RTL is synthesis-friendly or needs any updates.

P.S. It also gives you the ability to run synthesis on the reference RTL solutions provided for all problems!

I’m excited to see how this helps you write cleaner, synthesis-friendly RTL directly on the platform!

Have a great week!
Rahul