If you have worked with a valid-ready protocol or any of the traditional AMBA protocols then you must have heard about Skid Buffers. The skid buffers are a common design block but can be tricky to get right on the first try. The common usage of these buffers is as the pipelining flops for the valid-ready protocol, helping to break the timing path on the ready interface without losing performance.

Adding a pipeline stage on the ready signal is a simple solution however, it breaks the valid/ready protocol.

The issue with inserting a flop on the ready signal is that it alters the cycle at which the ready signal is observed by the requester and the completer. The completer asserts the ready signal and accepts the payload in the same cycle, while the requester holds the valid and payload signals for an additional cycle, as it samples the ready signal a cycle later.

This misalignment can introduce more bugs in the valid/ready protocol, as seen in the waveform below:

In the above waveform, the signals in yellow are the requester side of signals (usually called the ingress side) and the signals in orange are the completer side of signals (called the egress side). With the ready getting asserted a cycle before (signal: e_ready_i) the ready on the ingress side is seen a cycle later (signal: i_ready_o). This leads to an incorrect transfer on the requester side which ultimately leads to a missed (or a dropped) transaction on the completer's end and also a protocol violation where the valid on the completer side gets de-asserted without a ready.

How are these bugs avoided? Well, Skid Buffers are the answer. The skid buffer basically breaks the path on the ready signal without disrupting the valid/ready protocol. As the name suggests it buffers the transactions between the ingress and egress ports without dropping any data or breaking the protocol rules.

Skid Buffers are everywhere!

I was curious if any open source RISC-V implementations use skid buffers and found plenty in the famous Ibex Core. Ibex is a 32-bit pipeline RISC-V processor and uses skid buffers in multiple places. One of the usage is to break the feedthrough path from the grant from the instruction decode stage to the miss request sent on the interconnect. A direct combinational path from the grant to the output request isn’t ideal hence using the skid buffer helps to break this dependency. I also see this being used as one of the buffers to hold the 16b data incase the uncompressed instruction is misaligned. The skid buffer can provide the data if the uncompressed instruction isn’t aligned or could bypass it if there’s a compressed instruction (hence no loss in performance).

Want to learn more about Skid Buffers?

I have a one-hour video that discusses the design and line-by-line RTL implementation of skid buffers. This is part of the Hands-on RTL Design course, taken by over 1,000 engineers worldwide. The module not only introduces skid buffers but also lets you design and verify one by integrating it into a valid-ready protocol!

Well, that's it for this edition of the SiliconNotes. Have a great week!
Rahul