In this edition of the newsletter I want to focus on using Python for Design Verification.
The design verification space shares many similarities with the testing challenges encountered in the software industry. Our verification methodologies draw significant inspiration from the software world, and we've successfully adapted proven practices from software testing to enhance our processes. Our verification engineers can design Testbenches in SystemVerilog following the best coding practices. However, using SystemVerilog for verification has few challenges:
- New graduates often encounter discomfort with the language syntax, leading to a learning curve when utilizing SystemVerilog for verification.
- Simulating all verification features of the language reliably requires access to a commercial simulator, presenting a significant challenge.
This is why experts believe Python could facilitate a significant "shift left" in the Verification industry. With an abundance of freely available online resources, individuals can quickly learn Python and utilize open-source simulators to simulate testbenches. With a lot of us having a hands-on design verification engineer we would not only design Testbenches quickly but would be more confident in closing our designs with coverage.
So the question is - how can we use Python for Design Verification. Here's where the python library called "Cocotb" comes into action.
Cocotb
Cocotb is (as shared on their Github page):
cocotb is a coroutine based co-simulation library for writing VHDL and Verilog testbenches in Python.
Simply put, it allows us to design Testbenches using Python (and all of its helpful features) and does all of the dirty work of integrating with simulators in the backend. Leaving the engineers to focus on writing the testcases to hit those tricky corner bugs while the rest is handled by the library. Like I said before we could easily get started it with once we have the following tools installed in our System (I've successfully installed all of this on MacBook Air M1 and as well as on Ubuntu Machine):
- Python 3.6+
- GNU Make 3+
-
An HDL simulator
- I've successfully tested it on iverilog and Verilator
Once we have the above tools installed, we could simply do the following to get the cocotb python library:
That's it, we could now start experimenting with Cocotb by Verifying a D flip-flop. Let's take a quick look at the RTL:
// _Dff_
module dff (
input logic clk,
input logic d,
output logic q
);
always_ff @(posedge clk) begin
q <= d;
end
endmodule
The above RTL implements a standard D-ff using the d pin as the input port and the q pin as the output. This is implemented using the always_ff block using the non-blocking assignments. Let's try using the Python based testbench to verify this design.
The first thing we need to do in order to test the design is to generate stimulus and the clock. Using cocotb, we could easily use the random python library and then get the stimulus generated randomly. The clock on the other hand could be generated by using the already available cocotb.clock python class. Here's a snippet of how it is done:
# test_dff.pyimport random
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
@cocotb.test()asyncdef dff_simple_test(dut):"""Test that d propagates to q"""# Set initial input value to prevent it from floating
dut.d.value = 0
clock = Clock(dut.clk, 10, units="us") # Create a 10us period clock on port clk# Start the clock. Start it low to avoid issues on the first RisingEdge
cocotb.start_soon(clock.start(start_high=False))
# Synchronize with the clock. This will regisiter the initial `d` valueawait RisingEdge(dut.clk)
expected_val = 0# Matches initial input valuefor i in range(10):
val = random.randint(0, 1)
Alright, I believe this is getting too long, so I’ll stop here and add the missing details next week.
Well, that's it for this edition of the SiliconNotes.
Have a great week!
Rahul