In this edition of the newsletter, I want to revisit my list of must-have open-source tools for RTL Design and Verification and share how they have helped me become a better engineer.
Let's dive in 🤿
RTL Design & Verification
I've been using verilator for the past few years and I've used for most of my personal projects.
Verilator is an open-source tool which converts Verilog and SystemVerilog hardware description language (HDL) designs into a C++ or SystemC model that, after compiling, can be executed.
Verilator is not a traditional simulator but a compiler. However, I treat it as a simulator and haven’t encountered many difficulties in writing synthesizable RTL code. In fact, I’ve used Verilator internally for developing and verifying most of the designs in the Hands-on RTL Design Program. The SystemVerilog support for synthesizable RTL is robust and support for verification features is also being added.
Verilator has been in constant development over the past few years and the developers have done a brilliant job in adding support for SystemVerilog. I believe verilator is likely the first open-source simulator capable of simulating UVM testbenches. However, the support for running complex UVM testbenches is still under development but I believe it has reached a point where standard SystemVerilog class based testbenches could be easily developed.
Cocotb Testbench used with different HDLs
Personally, I've been using Verilator with the Cocotb package for verifying my RTL Designs. With Cocotb I can easily write the testbench in python and use it for verifying the designs. I've enjoyed using Cocotb especially because it can be used across designs written in various HDLs.
Formal Verification & Synthesis
This next tool has helped me write assertions for formal property verification and as well as running synthesis for my RTL Designs. Yep, I am talking about the Yosys open-source tool.
Yosys is a framework for RTL synthesis and more. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains
Combining yosys with SymbiYosys (sby) you could use yosys for formal proofs. It currently has support for the following:
Unbounded and bounded verification of safety properties
Unbounded verification of liveness properties
Reachability-check and bounds-detection for cover properties
Additional attributes for management of unconstrained signals
Synchronous, asynchronous, and multi-clock designs, resets and latches
SymbiYosys integrates with state-of-the-art SMT solvers and HW model checkers however few of the above mentioned features aren't supported in the freely available version of sby.
Combining Yosys with the UHDM plugin makes it possible to use SystemVerilog based RTL with the tool. I've been using it to test my designs and also to run synthesis. In fact, the YARP core was synthesized using Yosys and I was able to use openROAD to get it through detailed routing stage.
YARP RISC-V Core
I am a big believer in the power of open source tools and personally I've been using them daily for hands-on learning. If you are working as a RTL Design or Verification engineer then I'd strongly recommend getting the above tools installed. These have provided me with invaluable practical insights into RTL Design and Verification. Having the ability to compile, simulate and do synthesis on your own design quickly can be very useful and help in improving understanding of the entire flow.
Well, that's it for this edition of the SiliconNotes.