In this edition of the newsletter, I will continue discussing the use of Python for Design Verification.
In the last newsletter, we created a Cocotb-based testbench to verify a simple D flip-flop RTL, as shown:
The above RTL implements a standard D-ff using the d pin as the input port and the q pin as the output. This is implemented using the always_ff block using the non-blocking assignments.
And this is what we had for our python based testbench using Cocotb:
Great, we now have the RTL design and the Testbench coded. The next thing is to compile both together and let cocotb simulate the design along with the testbench. For this, cocotb already provides a set of makefiles which are created for various simulators and can be used for managing the infra on how the design and testbench are simulated. Here's a look at the makefile which would allow us to compile both the testbench and design and simulate it using cocotb:
Since most of the setup is already available in the Makefile.sim file, we just needed to pass the VERILOG_SOURCES, TOPLEVEL_LANG, MODULE and the TOPLEVEL makefile variables to have the simulation setup. Now, we could just run it by doing the following on the terminal:
That's it - the above would simulate the design using the python testbench. In the next post we would add how can we monitor the RTL outputs and also check whether the output matches the TB expectation. Until then try out the above design and testbench and share your output!
Well, that's it for this edition of the SiliconNotes.
Have a great week!
Rahul