Welcome to SiliconNotes!

In this edition of the newsletter, I want to share my recent experience with constraint randomization using Verilator. Verilator is an open-source simulator that is gradually adding support for various verification features including classes, assertions and even constraint randomization. I recently learned that Verilator now supports conditional constraints such as using if-else trees within the constraints. In my opinion this is a significant addition that will enable the development of constraints to cover a wide range of use cases.

Initial testing...

The first thing I did was to pull the latest verilator changes into my local repository and checkout the 5.028 release tag.

After checking out the 5.028 release tag I wanted to build verilator from source. The verilator installation guide gives all the steps necessary for building verilator on a linux machine. It took me about 5-10 minutes to complete the build and install the binary on my machine. After that, I quickly checked the version to confirm that everything was working properly.

Once done I was able to run the supplied tests and all of those quickly passed. This got me excited and I wanted to do develop something useful using this setup.

Legal RISC-V Instructions

One of the problems I faced while working on my RISC-V Processor Design course was generating stimulus for the top module. The stimulus relied on using an assembly program that needed to be assembled after which the instruction hex opcodes were extracted. This process felt tedious and I was too lazy to develop an instruction hex generator for it.

That got me thinking—it wouldn’t be too difficult to write a set of constraints for the RV32I instruction fields and use them to generate legal RISC-V instructions.

This idea worked well since there are only a few limited valid opcode values which formed the entire RV32I set and can easily be specified. The only thing remaining now was to add constraints such that the randomization picks any random value from the legal set and constructs the entire 32-bit instruction.

The following constraints was all what I needed to generate legal RV32I instructions:

The package file defined the legal values as enums so that the constraints could pick those up easily as shown:

After adding the constraints I just needed to construct the 32-bit instruction field in the `post_randomize()` method. Adding a few display statement in there too gave me a quick way to generate legal RV32I instructions randomly. Here's how the output looks like:

What's next...

I was amazed how quickly I was able to get all of this working. A big thanks to the way open source tools are growing.

I plan to use the above generator for the testing the YARP CPU further. This would form the basis of randomized tester which I plan to use for the 5-stage pipelined design version of the YARP core too.

Well, that's it for this edition of the SiliconNotes.

Have a great week!
Rahul