My list of top 10 RTL Design and Verification related projects to make your resume stand out!
Over the years, I’ve had the opportunity to interview multiple candidates for various positions, ranging from intern to leadership roles. Apart from their contributions at work, I also like to see personal or academic projects. I like to do this especially for candidates with less than 3-4 years of experience. This is because often we can’t really describe our work in great depth, but we can go as deep as we want with our projects.
How many of these have you covered?
I for one enjoy doing as it usually turns out to be a learning experience for me and gives me a reason to look forward to otherwise mundane interviews. Given this, I see some of the resumes really stand out due to great Design and Verification projects. Here are my top 10: 1️⃣ RISC-V Processor Design - You can’t really miss this one 2️⃣ N-Way Set Associative Virtually Index and Physically Tagged Cache Design - Click here to learn about LRU replacement scheme! 3️⃣ Modeling and comparing various Branch Prediction Algorithms 4️⃣ UVM verification of a Bitcoin Hasher 5️⃣ Modeling Superscalar OoO Pipeline - I am yet to see someone do it using synthesisable RTL 6️⃣ Designing a simple Convolutional Neural Network 7️⃣ Formal/Functional verification of a RISC-V Processor 8️⃣ Modelling Snoop-based Cache Coherency scheme - People usually cover MOSI//MOESI 9️⃣ UVM Testbench and coverage closure for AXI Interface based design ⚡ Designing a system using Credit based Valid-Ready Protocol with retry support How many of these have you covered? PS: If you are interested in few of these projects, checkout my Hands-on Design courses: RTL Design course (covers 3 projects from the list):