The case of LUI Instruction 🔎


SiliconNotes

​Read on web →

Welcome to SiliconNotes!

I was reviewing the RV32I instruction set when I stumbled upon the LUI instruction and realized I had completely forgotten why this instruction exists. I spent some time reading about it in the RISC-V Unprivileged Specifications and thought I would share my findings today.


What is the LUI Instruction?

The Load Upper Immediate (LUI) instruction is a simple instruction but serves a very important function in RISC-V cores. âš¡

When I first read about the instruction, I wasn’t sure why and how this instruction would be used other than just loading immediate values into the architectural registers. The hardware implementation of the instruction also adds an extra leg either in the mux going to the ALU or in the mux used for selecting write data into the register.

But once I started implementing the YARP core and was writing RISC-V assembly programs, I realized how useful the LUI instruction really is. Working with 32-bit addresses, I wanted the JALR instruction to jump across various regions of the program, and this is where I was able to make use of the LUI instruction.

The target address for the JALR instruction is obtained by adding the sign-extended 12-bit I-immediate to the register rs1. Now, to jump anywhere in a 32-bit absolute address range, an LUI instruction can be used.

An LUI instruction can first load rs1 with the upper 20 bits of a target address; then JALR can add in the lower bits and jump anywhere in a 32-bit pc-relative address range.

What's next?

Do you know if there’s another way (or instruction) which, when paired with JALR, can allow us to jump anywhere in a 32-bit pc-relative address range?

Hint: It is very similar to the LUI instruction :). Reply me if you know about this instruction. But if you don't and are interested in learning about the RISC-V architecture in the right way. I would recommend checking out my hands-on RISC-V Processor Design Course.

This course will help you cover the unprivileged RISC-V Instruction Set Architecture, ensuring your fundamentals are strong. The course also includes hands-on exercises to design your very own RISC-V based single-cycle processor from scratch in SystemVerilog!

PS: We are running a massive limited time discount offer. Use referral code: QS-DIWALI24 to get 20% off!


Well, that's it for this edition of the SiliconNotes.

Have a great week!
Rahul


#103 Sector D, Jammu, 180011
​Update your email preferences or unsubscribe here​