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Do you know when to use System Verilog unique case vs priority case? Let’s take a closer look👇
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SystemVerilog provides the unique and priority keyword to cleanly describe how logic should be synthesised. These are commonly used along the case statement but one could even add the unique keyword to an if-else-if tree. But how does adding unique or priority keyword help?

Adding the unique keyword implies that the case statement can be evaluated in parallel, similarl to an and-or tree. While the priority keyword ensures that each case statement is evaluated in the order it's listed, indicating a priority. When using the priority keyword, any unlisted statements are considered don't cares, allowing the synthesis tool to optimise them.

What do you think will happen if the priority case includes a default statement?
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A unique case should be used when the case statements can’t overlap and don’t have associated priorities, while a priority case is suitable for inferring priority logic.
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Interested in learning more? Checkout my Hands-on RTL Design course at QuickSilicon for deeper insights into micro-architectural and RTL Design: quicksilicon.in​

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Well, that's it for this edition of the SiliconNotes.

Have a great week and a very Happy New Year!
Rahul